The integrated circuit (“IC”) industry faces the challenge of reducing yield loss caused by defects during manufacturing. These defects can be either random defects or systematic defects. Random defects, as the name implies, result from random occurrences such as particulate contamination. Systematic defects are non-random and result from problems with the manufacturing process and/or IC design. Systematic defects will recur when a manufacturer uses a similar process or IC pattern. A designer may be able to categorize or anticipate certain systematic defects based on a shape or feature pattern on an IC.
To aid in diagnosing the root causes of defects, companies have developed tools to simulate faults generated by the defects in digital ICs. These tools help designers and/or manufacturers reduce the number of defects in digital ICs and thereby reduce yield loss. However, these tools conduct logic-level simulations which are inapplicable to analog circuitry. In the past, circuit designers focused on ICs with mainly digital circuitry, so there were relatively few analog circuitry faults to diagnose. Thus, a designer could diagnose faults in analog circuitry through in-line inspection.
Today, the IC industry is developing more and more mixed signal ICs with substantial amounts of analog circuitry. The IC industry is also moving to smaller and smaller IC features. Manufacturing mixed signal ICs with sub-90 nm processes have many subtle design-process variations which increase the types of systematic defects present in analog circuitry. As a result, designers are unable to adequately diagnose all of the new defect types using in-line inspection. Designers, therefore, need a better tool for diagnosing faults in analog circuitry.